Introduction to Computer Architecture and Machine-Level Programming

Course
Course Catalog URL: 
http://catalog.iastate.edu/azcourses/com_s/
Identifier: 
COM S 3210
Professor(s): 
Jeremy Sheaffer

Offered during Fall and Spring Semesters each year.

  1. Credits and contact hours: 
  2. Instructor’s or course coordinator’s name: Jeremy Sheaffer
  3. Text book, title, author, and year: 
  4. Other supplemental materials: 

Specific course information

  1. Brief description of the content of the course: 
  2. Prerequisites or co-requisites: 
  3. Required, elective, or selected elective? 

Specific goals for the course

  1. Specific outcomes of instruction:
  • An ability to analyze a problem and identify and define the computing requirements appropriate to its solution. (1)
  • An ability to design, implement, and evaluate a computer-based system, process, component or program to meet desired needs. (2)
  • An ability to apply mathematical foundations, algorithmic principles, and computer science theory in the modeling and design of computer-based systems that demonstrate comprehension of the tradeoffs involved in design choices. (6)

Brief list of topics to be covered

  • Chapter 1: Computer abstractions and technology: Measuring and evaluating performance, metrics of performance, cost/benefit tradeoffs, instruction count, CPI, clock cycle time, comparing and summarizing performance, the switch from uniprocessors to multiprocessors (Sec 1.8), Amdahl's law (Sec 1.10)
  • Chapter 2: Instructions: Language of the Computer: Instruction set architecture and assembly language of LEGv8, signed and unsigned numbers, representing instructions - the LEGv8 instruction set, instructions for decision making, arithmetic and logical operations, arithmetic overflow, Parallelism and instructions: synchronization (Sec 2.11), a sorting example
  • Chapter 3: Arithmetic for Computers: Addition and subtraction, multiplication, division, parallelism and computer arithmetic (Sec 3.6), Streaming SIMD extensions (Sec 3.7)
  • Chapter 4: The Processor: Building a datapath, pipelining, pipelined datapath and control, hazards in pipelining, exceptions (Sec 4.9), parallelism via instructions (Sec 4.10)
  • Chapter 5: Large and fast: exploiting memory hierarchy: A framework for memory hierarchies, the basics of caches, Placement, replacement, and memory interaction policies, Virtual machines and virtual memory, parallelism and memory hierarchy: cache coherence (Sec 5.10)
  • Chapter 6: Introduction to GPUs.