AKHILESH TYAGI AKHILESH TYAGI (tyagi@cs.iastate.edu)

Associate Professor of Electrical and Computer Engineering, and
Adjunct Associate Professor of Computer Science, at Iowa State University.

Major Interests

VLSI: Algorithms, CAD Tools, Automatic generation of VLSI modules and systems for low power/energy; VLSI architectures.
Computer Architecture: Branch-decoupled architectures and instruction-level parallelism.
Complexity Theory: VLSI complexity Theory; Energy complexity.

Representative Publications

Energy Consumption in Multilective and Boundary VLSI Computations, IEEE Journal of Solid State Circuits, September 1991.

A Reduced Area Scheme for Carry-Select Adders, IEEE Transactions on Computers, October 1993.

Statistical Module-Level Area and Delay Estimation, in VLSI Design, April 1997.

Entropic Limitations on Finite State Machine Switching, in IEEE Transactions on VLSI Systems, December 1997.

Efficient Algorithms for Optical Computing with the DFT Primitive (with John Reif), in Applied optics, October 1997. A preliminary version in Proceedings of the Tenth Conference on Foundations of Software Technology & Theoretical Computer Science, December 1990, Lecture Notes in Computer Science 472, Springer-Verlag.

An Optical Delay-Line Memory Model with Efficient Algorithms (with John Reif), in Optical Engineering, The Journal of SPIE , September 1997. A preliminary version appears in ADVANCED RESEARCH in VLSI: Proceedings of the 1991 International Conference, MIT Press, March 1991.

Energy Complexity and Delay Comparison of Dynamic and Static PLA Design Styles, in ADVANCED RESEARCH IN VLSI : Proceedings of the 1987 Stanford Conference, MIT Press, March 1987.

Energy Time Trade-offs in VLSI Computations, in Proceedings of the Ninth Conference on Foundations of Software Technology & Theoretical Computer Science, Lecture Notes in Computer Science #405, Springer-Verlag, December 1989, a revised version submitted to IEEE Transactions on Computers.

On Probabilistic Switch-Level Simulation for Asynchronous Circuits (with Suresh Rajgopal), Proceedings of the 2nd IEEE European Design Automation Conference, February 1991, pp. 339-343.

A Principle of Least Computational Action, Proceedings of IEEE Workshop on Physics and Computation (PhysComp '92), IEEE Computer Society Press, October 1992, pp. 262-266.

VLSI Design Parsing, Proceedings of the IEEE International Conference on Computer-Aided Design, November 1992.

A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation, Proceedings of the Sixth International Conference on VLSI Design,
IEEE Computer Society Press, January 1993.

Encoded Arithmetic for Reversible Logic, Proceedings of IEEE Workshop on Physics and Computation (PhysComp '94), IEEE Computer Society Press, November 1994.

Re-Encoding for Low Power State Assignment of FSMs (with Vamsi Veeramachaneni and Suresh Rajgopal), Proceedings of the 1995 ACM International Symposium on Low Power Design, April 1995.

EPNR: Energy Efficient Layout Synthesis (with Glenn Holt), Proceedings of the IEEE International Conference on Computer Design (ICCD '95), October 1995.

Entropic Bounds on FSM Switching, Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design, IEEE Computer Society Press, August 1996.

GEEP: A Low Power Genetic Algorithm Layout System (with Glenn Holt), Proceedings of IEEE Midwest Symposium on Circuits and Systems, August 1996.

Integrated Area-Power Optimal State Assignment, Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI '96), November 1996.

Branch Decoupled Architectures, Proceedings of the Workshop on Interaction between Compilers and Computer Architectures at the IEEE High Performance Computer Architecture Symposium, February 1997. A summary to appear in the Newsletter of IEEE TC on Computer Architecture.

Low-Power FSM Design using Huffman-Style Encoding (with Prasoon Surthi and Liang-Fang Chao), Proceedings of European Design and Test Conference, IEEE Computer Society Press, March 1997.

Minimizing Interconnect Energy through Integrated Low-Power Placement and Combinational Logic Synthesis (with Glenn Holt), Proceedings of ACM International Symposium on Physical Design, April 1997.

Reconfigurable Memory Queues/Computing Units Architecture, Proceedings of the Reconfigurable Architectures Workshop at the International Parallel Processing Symposium, April 1997.