This tutorial introduces undergraduate students to computer architecture concepts of caches and pipelining . It contains examples, interactive applets and some problems with solutions to illustrate basic ideas. For more information on the topics the interested reader is referred to "Computer Architecture: A Quantitative Approach", second edition, by D.A.Patterson and J.L.Hennessy. The problems that have been solved have been taken from a number of sources but the solutions are novel and unique in the sense that emphasis has been placed not only on the answers but also on reasoning processes that will be useful in solving similar problems.
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Feedback consisting of comments and errors are welcome, and can be e-mailed to Gurpur Prabhu at prabhu@cs.iastate.edu.
Topics
Computer Performance
Computer Performance - II
Principles and Levels
Make the Common Case Fast
Amdahl's Law
Principle of Locality
Smaller is Faster
Common Questions
Block Placement
Placement Methods
Examples
Block Identification
Address Structure
Examples
Block Replacement
Policies
Interactive applet to check different policies
Example (a problem)
Interaction with Memory
On Read
On Write
Interactive Diagram
Example (a problem)
Pipelining
Classification of Instruction Sets
Addressing Modes
Memory Interpretation
Memory Alignment
DLX architecture
Instruction Set
Instruction Layout
Examples of Instructions
An Implementation of DLX
The Basic Pipeline for DLX
Performance Issues in Pipelining
Pipeline Hazards
Performance in Pipeline with Stalls
Structural Hazards
Data Hazards
Forwarding
Data Hazard Classification
When Stalls are Required
Pipeline Scheduling
Control Hazards
Branch Prediction Schemes
Predict Not Taken
Delayed Branch
Cancelling Branch
Problem on Branch Prediction Schemes
Problem on Pipeline Hazards
Dealing with Exceptions
Types of Exceptions
Exceptions in DLX
Pipeline with Multicycle Operations
Instruction Level Parallelism
Loop Unrolling
Dynamic Scheduling Techniques