Structural
Hazards
When a machine is pipelined, the overlapped execution of instructions
requires pipelining of functional units and duplication of resources to
allow all posible combinations of instructions in the pipeline.
If some combination of instructions cannot be accommodated because
of a resource conflict, the machine is said
to have a structural hazard.
Common instances of structural hazards arise when
Some
functional unit is not fully pipelined. Then a sequence of instructions
using that unpipelined unit cannot proceed at the rate of one per clock
cycle
Some
resource has not been duplicated enough to allow all combinations
of instructions in the pipeline to execute.
Example1:
a machine may have only one register-file write port, but in some cases
the pipeline might want to perform two writes in a clock cycle.
Example2:
a machine has shared a single-memory pipeline for data and instructions.
As a result, when an instruction contains a data-memory reference(load),
it
will conflict with the instruction reference for a later instruction (instr
3):
| Clock cycle number |
| Instr |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
| Load |
IF |
ID |
EX |
MEM |
WB |
|
|
|
| Instr 1 |
|
IF |
ID |
EX |
MEM |
WB |
|
|
| Instr 2 |
|
|
IF |
ID |
EX |
MEM |
WB |
|
| Instr 3 |
|
|
|
IF |
ID |
EX |
MEM |
WB |
To resolve this, we stall the pipeline for one clock cycle when a data-memory
access occurs. The effect of the stall is actually to occupy the resources
for that instruction slot. The following table shows how the stalls are
actually implemented.
| Clock cycle number |
| Instr |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
| Load |
IF |
ID |
EX |
MEM |
WB |
|
|
|
|
| Instr 1 |
|
IF |
ID |
EX |
MEM |
WB |
|
|
|
| Instr 2 |
|
|
IF |
ID |
EX |
MEM |
WB |
|
|
| Stall |
|
|
|
bubble |
bubble |
bubble |
bubble |
bubble |
|
| Instr 3 |
|
|
|
|
IF |
ID |
EX |
MEM |
WB |
Instruction 1 assumed not to be data-memory reference (load or store),
otherwise Instruction 3 cannot start execution for the same reason as above.
To simplify the picture it is also commonly shown like this:
| Clock cycle number |
| Instr |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
| Load |
IF |
ID |
EX |
MEM |
WB |
|
|
|
|
| Instr 1 |
|
IF |
ID |
EX |
MEM |
WB |
|
|
|
| Instr 2 |
|
|
IF |
ID |
EX |
MEM |
WB |
|
|
| Instr 3 |
|
|
|
stall |
IF |
ID |
EX |
MEM |
WB |
Introducing stalls degrades performance as we saw before.
Why, then, would the designer allow structural hazards? There are two reasons:
To
reduce cost. For example, machines that support both an instruction
and a cache access every cycle (to prevent the structural hazard of the
above example) require at least twice as much total
memory.
To
reduce the latency of the unit. The shorter latency comes from the
lack of pipeline registers that introduce overhead.