Now we are ready to consider the challenges of exceptional situations where the instruction execution order is changed in unexpected ways.
Exceptional situations are harder to handle in a pipelined machine because the overlapping of instructions makes it more difficult to know whether an instruction can safely change the state of the machine.
In a pipelined machine an instruction is executed step by step and is not completed for several clock cycles. Unfortunately, other instructions in the pipeline can raise exceptions that may force the machine to abort the instructions in the pipeline before they complete.
First we look at the types of situations that can arise and what architectural requirements exist for supporting them.