| Instruction type/opcode | Instruction meaning |
| Data transfers | Move data between registers and memory, or between the integer and FP or special register; only memory address mode is 16-bit displacement + contents of a GPR |
| LB, LBU, SB | Load byte, load byte unsigned, store byte |
| LH, LHU, SH | Load halfword, load halfword unsigned, store halfword |
| LW, SW | Load word, store word (to/from integer registers) |
| LF, LD, SF, SD | Load SP float, load DP float, store SP float, store DP float (SP - single precision, DP - double precision) |
| MOVI2S, MOVS2I | Move from/to GPR to/from a special register |
| MOVF, MOVD | Copy one floating-point register or a DP pair to another register or pair |
| MOVFP2I, MOVI2FP | Move 32 bits from/to FP tegister to/from integer registers |
|
Arithmetic / Logical |
Operations on integer or logical data in GPRs; signed arithmetics trap on overflow |
| ADD, ADDI, ADDU, ADDUI | Add, add immediate (all immediates are 16-bits); signed and unsigned |
| SUB, SUBI, SUBU, SUBUI | Subtract, subtract immediate; signed and unsigned |
| MULT, MULTU, DIV, DIVU | Multiply and divide, signed and unsigned; operands must be floating-point registers; all operations take and yield 32-bit values |
| AND, ANDI | And, and immediate |
| OR, ORI, XOP, XOPI | Or, or immediate, exclusive or, exclusive or immediate |
| LHI | Load high immediate - loads upper half of register with immediate |
| SLL, SRL, SRA, SLLI, SRLI, SRAI | Shifts: both immediate(S__I) and variable form(S__); shifts are shift left logical, right logical, right arithmetic |
| S__, S__I | Set conditional: "__"may be LT, GT, LE, GE, EQ, NE |
|
Control |
Conditional branches and jumps; PC-relative or through register |
| BEQZ, BNEZ | Branch GPR equal/not equal to zero; 16-bit offset from PC |
| BFPT, BFPF | Test comparison bit in the FP status register and branch; 16-bit offset from PC |
| J, JR | Jumps: 26-bit offset from PC(J) or target in register(JR) |
| JAL, JALR | Jump and link: save PC+4 to R31, target is PC-relative(JAL) ot a register(JALR) |
| TRAP | Transfer to operating system at a vectored address |
| RFE | Return to user code from an exception; restore user code |
|
Floating point |
Floating-point operations on DP and SP formats |
| ADDD, ADDF | Add DP, SP numbers |
| SUBD, SUBF | Subtract DP, SP numbers |
| MULTD, MULTF | Multiply DP, SP floating point |
| DIVD, DIVF | Divide DP, SP floating point |
| CVTF2D, CVTF2I, CVTD2F,
CVTD2I, CVTI2F, CVTI2D |
Convert instructions: CVTx2y converts from type x to type y, where x and y are one of I(Integer), D(Double precision), or F(Single precision). Both operands are in the FP registers. |
| __D, __F | DP and SP compares: "__" may be LT, GT, LE, GE, EQ, NE; set comparison bit in FP status register. |