The architecture of DLX was chosen based on observations about most frequently used primitives in programs. DLX provides a good architectural model for study, not only because of the recent popularity of this type of machine, but also because it is easy to understand.
Like most recent load/store machines, DLX emphasizes

A simple load/store instruction set
Design for pipelining efficiency
An easily decoded instruction set
Efficiency as a compiler target

thirty-two 32-bit general purpose registers (GPRs), named R0, R1, ..., R31. The value of R0 is always 0.
thirty-two floating-point registers (FPRs), which can be used as

32 single precision (32-bit) registers or
even-odd pairs holding double-precision values. Thus, the 64-bit FPRs are named F0,F2,...,F30

a few special registers can be transferred to and from the integer registers.

for integer data

-  8-bit bytes
- 16-bit half words
-  32-bit words

for floating point

-  32-bit single precision
-  64-bit double precision

The DLX operations work on 32-bit integers and 32- or 64-bit floating point. Bytes and half words are loaded into registers with either zeros or the sign bit replicated to fill the 32 bits of the registers.

byte addressable
Big Endian mode
32-bit address
two addressing modes (immediate and displacement). Register deferred  and absolute addressing with 16-bit field are accomplished using R0.
memory references are load/store between memory and GPRs or FPRs
access to GPRs can be to a byte, to a halfword, or to a word
all memory accesses must be aligned
there are instructions for moving between a FPR and a GPR

instruction layout for DLX
complete list of instructions in DLX
32 bits(fixed)
must be aligned

Operations

There are four classes of instructions:

Load/Store
Any of the GPRs or FPRs may be loaded and stored except that loading R0 has no effect.

ALU Operations
All ALU instructions are register-register instructions.
The operations are :
 - add
 - subtract
 - AND
 - OR
 - XOR
 - shifts
Compare instructions compare two registers (=,!=,<,>,=<,=>).
If the condition is true, these instructions place a 1 in the destination register, otherwise they place a 0.

  Branches/Jumps
All branches are conditional.The branch condition is specified by the instruction, which may test the register source for zero or nonzero.

Floating-Point Operations
- add
- subtract
- multiply
- divide