Example on interaction with main memory

Consider a computer with the following features:

90% of all memory accesses are found in the cache (hit ratio = 0.9);
The block size is 2 words and the whole block is read on any miss;
The CPU sends references to the cache at the rate of 107 words per second;
25% of the above references are writes (writes = 25%, reads = 75%);
The bus can support 107 words per second, read or writes (total bus bandwidth = 107);
The bus reads or writes a single word at a time;
Assume at any one time, 30% of the block frames in the cache have been modified;
The cache uses write allocate on a write miss.
 
You are considering adding a peripheral to the bus, and you want to know how much of the bus bandwidth is already used. Calculate the percentage of the bus bandwidth used on the average in the two cases below. This percentage is called the traffic ratio. State any further assumptions you need, if any.

a) The cache is write through.
 
Bus Bandwidth Used Reasoning
Read hit 0 Hit means reference is found in cache, so no bus bandwidth used
Read miss 107 * 0.1 * 0.75 * 2 miss ratio = 1- hit ratio = 1 - 0.9 = 0.1 
reads are 75% of total number of references 
block size = 2 words
Write hit 107 * 0.9 * 0.25 * 1 Because we have write through policy we have to write to main memory on every hit. But we have to write only 1 word. 
Writes are 25% of total number of references, 
hit ratio = 0.9
Write miss 107 * 0.1 * 0.25 * (2+1) On every write miss we have to load a block (2 words) to cache because of write allocate policy, and write 1 word ( the word to write from CPU) because of write through policy.
Writes are 25% of total number of references, 
hit ratio = 0.9

Total Bandwidth Used = BW used on Read hit
                                           ;   + BW used on Read miss
                                           ;   + BW used on Write hit
                                           ;   + BW used on write miss
                                           ; = 0 + 107 * 0.1 * 0.75 * 2 +107 * 0.9 * 0.25 * 1 + 107 * 0.1 * 0.25 * (2+1)
                                           ; = 107 * 0.45

Total Bandwidth Used        107 * 0.45
----------------------------  =  -------------  = 0.45
       Total Bandwidth                107
 

b) The cache is write back.
 
 
Bus Bandwidth Used Reasoning
Read hit 0 Hit means reference is found in cache, so no bus bandwidth used
Read miss 107 * 0.1 * 0.75 * [ 2 * 0.3 + 2] miss ratio = 1- hit ratio = 1 - 0.9 = 0.1 
reads are 75% of total number of references 
writes are 25% of total number of references 
block size = 2 words
*  The term 2*0.3 refers to replacing the dirty block (0.3 is the probability of the block to be dirty). We write back the dirty block (2 words) and read needed block (another 2 words).
Write hit 0 Write hit does not generate any traffic on the bus, just makes the block in cache dirty.
Write miss 107 * 0.1 * 0.25 * [2 * 0.3 + 2] On a write miss we have to load a block (2 words) to cache because of write allocate policy, 
and write a dirty block to main memory (2 * 0.3).

Total Bandwidth Used = BW used on Read hit
                                           ;   + BW used on Read miss
                                           ;   + BW used on Write hit
                                           ;   + BW used on write miss
                                           ; = 0 + 107 * 0.1 * 0.75 * [2 * 0.3 + 2] + 0 + 107 * 0.1 * 0.25 * [2 * 0.3 + 2]
                                           ; = 107 * 0.26

Total Bandwidth Used        107 * 0.26
----------------------------  =  -------------  = 0.26
       Total Bandwidth                107