Cache memory consists of two portions:

Directory
      -  Address Tags ( checked to match the block address from CPU )
      -  Control Bits ( indicate that the content of a block is valid )
RAM
      -  Block Frames ( contain data )

As a rule, all possible tags are searched in parallel because speed is critical.

Accordingly an address , generated by CPU has the following structure:

The block offset field selects the desired data (minimal addressable unit) from the block, the index field selects the set, and the tag field is compared against cache tag for a hit.

While the comparison could be made on more of the address than the tag, there is no need because:
     Checking the index would be redundant, since it was used to select the set to be checked.
     Checking the offset is unnecessary since the entire block is present or not, and hence all block offsets must match.